ICASSP99 DSP Chips, Architectures and Implementations

DSP Chips, Architectures and Implementations
Home Full List of Titles 1: Speech Processing CELP Coding Large Vocabulary Recognition Speech Analysis and Enhancement Acoustic Modeling I ASR Systems and Applications Topics in Speech Coding Speech Analysis Low Bit Rate Speech Coding I Robust Speech Recognition in Noisy Environments Speaker Recognition Acoustic Modeling II Speech Production and Synthesis Feature Extraction Robust Speech Recognition and Adaptation Low Bit Rate Speech Coding II Speech Understanding Language Modeling I 2: Speech Processing, Audio and Electroacoustics, and Neural Networks Acoustic Modeling III Lexical Issues/Search Speech Understanding and Systems Speech Analysis and Quantization Utterance Verification/Acoustic Modeling Language Modeling II Adaptation /Normalization Speech Enhancement Topics in Speaker and Language Recognition Echo Cancellation and Noise Control Coding Auditory Modeling, Hearing Aids and Applications of Signal Processing to Audio and Acoustics Spatial Audio Music Applications Application - Pattern Recognition & Speech Processing Theory & Neural Architecture Signal Separation Application - Image & Nonlinear Signal Processing 3: Signal Processing Theory & Methods I Filter Design and Structures Detection Wavelets Adaptive Filtering: Applications and Implementation Nonlinear Signals and Systems Time/Frequency and Time/Scale Analysis Signal Modeling and Representation Filterbank and Wavelet Applications Source and Signal Separation Filterbanks Emerging Applications and Fast Algorithms Frequency and Phase Estimation Spectral Analysis and Higher Order Statistics Signal Reconstruction Adaptive Filter Analysis Transforms and Statistical Estimation Markov and Bayesian Estimation and Classification 4: Signal Processing Theory & Methods II, Design and Implementation of Signal Processing Systems, Special Sessions, and Industry Technology Tracks System Identification, Equalization, and Noise Suppression Parameter Estimation Adaptive Filters: Algorithms and Performance DSP Development Tools VLSI Building Blocks DSP Architectures DSP System Design Education Recent Advances in Sampling Theory and Applications Steganography: Information Embedding, Digital Watermarking, and Data Hiding Speech Under Stress Physics-Based Signal Processing DSP Chips, Architectures and Implementations DSP Tools and Rapid Prototyping Communication Technologies Image and Video Technologies Automotive Applications / Industrial Signal Processing Speech and Audio Technologies Defense and Security Applications Biomedical Applications Voice and Media Processing Adaptive Interference Cancellation 5: Communications, Sensor Array and Multichannel Source Coding and Compression Compression and Modulation Channel Estimation and Equalization Blind Multiuser Communications Signal Processing for Communications I CDMA and Space-Time Processing Time-Varying Channels and Self-Recovering Receivers Signal Processing for Communications II Blind CDMA and Multi-Channel Equalization Multicarrier Communications Detection, Classification, Localization, and Tracking Radar and Sonar Signal Processing Array Processing: Direction Finding Array Processing Applications I Blind Identification, Separation, and Equalization Antenna Arrays for Communications Array Processing Applications II 6: Multimedia Signal Processing, Image and Multidimensional Signal Processing, Digital Signal Processing Education Multimedia Analysis and Retrieval Audio and Video Processing for Multimedia Applications Advanced Techniques in Multimedia Video Compression and Processing Image Coding Transform Techniques Restoration and Estimation Image Analysis Object Identification and Tracking Motion Estimation Medical Imaging Image and Multidimensional Signal Processing Applications I Segmentation Image and Multidimensional Signal Processing Applications II Facial Recognition and Analysis Digital Signal Processing Education Author Index A B C D E F G H I J K L M N O P Q R S T U V W X Y Z	Fast Implementation of Orthogonal Wavelet Filterbanks Using Field-Programmable Logic Authors: Uwe Meyer-Baese, Julien Buros, Wolfgang Trautmann, Fred Taylor, Page (NA) Paper number 2107 Abstract: Field-Programmable Logic (FPL) is on the verge of revolutionizing digital signal processing (DSP) in the manner that programmable DSP microprocessors did nearly two decades ago. While FPL densities and performance have steadily improved to the point where some DSP solutions can be integrated into a single FPL chip, they still have limited the use in high-precision high-bandwidth applications. In this paper it is shown that alternative implementation strategies can be found which overcome the precision/bandwidth barrier. The design of Daubechies length 4 and 8 filter is presented to compare FPL and programmable DSP solutions. IC992107.PDF (From Author) IC992107.PDF (Rasterized) TOP High-Performance FPGA Filters Using Sigma-Delta Modulation Encoding Authors: Chris H Dick, Fred Harris, Page (NA) Paper number 1195 Abstract: This paper investigates an architectural option for constructing high sample-rate narrow-band single rate and multi-rate filters using Xilinx field programmable gate array (FPGA) technology. Sigma-delta modulation encoding is applied to the input data in order to effect a reduction in the precision of the arithmetic units in the filter. This is done without compromising the signal integrity within the band of interest. The implementation provides a significant savings in device logic resources in comparison to other techniques that provide the same functionality. The sigma-delta pre-processor is described and its implementation using XC4000 FPGAs is reported. The architecture of the reduced precision filter is presented and its FPGA realization described. IC991195.PDF (From Author) IC991195.PDF (Rasterized) TOP AMD 3DNow! Vectorization for Signal Processing Applications Authors: Dongho Kim, Gwangwoo Choe, Page (NA) Paper number 2248 Abstract: AMD 3DNow! Technology provides substantial speedup for Digital Signal Processing applications. A set of DSP routines is vectorized with the 3DNow! technology. The simplicity of the vector unit makes it easier to convert the conventional DSP programs into vector operations, thus reduces the learning curve. The performance gain from typical DSP routines such as FIR, IIR and FFT indicates that the speedup can reach up to 1.5 comparing to the conventional host-based signal processing units. 3D games and multimedia applications benefit from the technology. The vectorization can be integrated into compilers for the ease of use in increasing the performance of the signal processing applications. IC992248.PDF (From Author) TOP Radix-4 FFT Implementation Using SIMD Multimedia Instructions Authors: Kouhei Nadehara, Takashi Miyazaki, Ichiro Kuroda, Page (NA) Paper number 2264 Abstract: In this paper, a fast radix-4 complex FFT implementation using 4-parallel SIMD instructions is presented. Four radix-4 butterflies are calculated in parallel at all stages by loading consecutive 4 elements into a register. At the last stage, every 4 elements is packed into a register and calculated in parallel. This regular data flow enables higher parallelism and an overhead reduction in data format conversion. The implementation result on the V830R processor, which has a 4-parallel SIMD-type multimedia instruction set, achieves practical performance quite competitive with high-end parallel DSPs. Multiply-accumulate instructions with symmetrical rounding introduced to the V830R processor are effective to maintain FFT accuracy. IC992264.PDF (From Author) IC992264.PDF (Rasterized) TOP Some Fast Speech Processing Algorithms using AltiVec Technology Authors: Sanjay M Joshi, University of Maryland Baltimore County, Baltimore, MD, USA (USA) Pradeep K Dubey, IBM Research Division, New Delhi, India (India) Page (NA) Paper number 1477 Abstract: The AltiVec technology is a SIMD (Single Instruction Multiple Data) extension to PowerPC architecture. It is intended to provide architectural support for performance improvement of various image and signal processing applications, including speech processing, on a general-purpose processor implementation, such as, the PowerPC line of processors. In this paper we have implemented some of the common speech processing algorithms on AltiVec architecture. The algorithms discussed in this paper are autocorrelation computation, linear prediction coefficients computation via Levinson-Durbin method and Schur recursion, and part of the GSM speech compression system. AltiVec obtained significant speedups on all these algorithms, compared to the scalar PowerPC implementation. We also found that additional speedup was achievable by porting to new, more SIMD-friendly algorithm. IC991477.PDF (From Author) IC991477.PDF (Rasterized) TOP A New Parallel DSP with Short-Vector Memory Architecture Authors: Jose Fridman, William C Anderson, Page (NA) Paper number 2317 Abstract: This paper presents a new highly-parallel DSP architecture based on a short-vector memory system developed at Analog Devices, Inc. This DSP incorporates for the first time in an embedded processor a number of techniques found in general-purpose computing, such as branch prediction, deep and fully-interlocked pipeline, and SIMD instruction execution. By means of its short-vector high-bandwidth memory system it is able to deliver sustained performance that is close to its peak computational rates of 1.5 GFLOPS (32-bit floating-point), or 6 BOPS (16-bit fixed-point). IC992317.PDF (From Author) IC992317.PDF (Rasterized) TOP FPGA Implementation of a Nonlinear Two Dimensional Fuzzy Filter Authors: Justin G.R. Delva, Department of Electrical Engineering and Computer Science, University of Wisconsin-Milwaukee (U.K.) Ali M Reza, Department of Electrical Engineering and Computer Science, University of Wisconsin-Milwaukee (U.K.) Robert D Turney, Page (NA) Paper number 2110 Abstract: Nonlinear filtering has found many practical applications in digital signal and image processing. The computation complexity of these filtering algorithms make them difficult for real-time hardware implementation. One of these nonlinear filters, which is based on fuzzy classification of each pixel to subgroups of its neighboring pixels, is considered here for hardware implementation. The criteria of this filter are based on the local context which form the basis of the fuzzy rule. The filtering algorithm is slightly modified for implementation into a Xilinx Virtex series of FPGA for real-time processing of image sequences. Implementation details and recommendations for further improvement are discussed. Result of a simulation example from the proposed hardware implementation is also presented. IC992110.PDF (From Author) IC992110.PDF (Rasterized) TOP