Title:    DSP System Design   (Poster)

Time: Friday, March 19, 1:00 PM - 3:00 PM

Location:    Exhibit Hall E 3

Chair: Vijay Jain    (University of Central Florida)

1:00 PM    DISPS-4.1
Low-Power DV Encoder Architecture for Digital CMOS Camcorder
Jeff Y Hsieh, Teresa H Meng (Stanford University)
[abstract]  [manuscript]

DISPS-4.2
High Performance and Cost Effective Memory Architecture for an HDTV Decoder LSI
Tetsuro Takizawa, Junji Tajime, Hidenobu Harasaki (C&C Media Research Laboratories, NEC Corporation)
[abstract]  [manuscript]

DISPS-4.3
A Programmable Processor with Multiple Functional Units and Banked Registers for General Purpose Numerical Processing
Takafumi Morifuji, Yoshinori Takeuchi, Masaharu Imai (Graduate School of Engineering Science, Osaka University)
[abstract]  [manuscript]

DISPS-4.4
Fast Construction of Test Program Generators for Digital Signal Processors
Shai Rubin, Moshe Levinger (IBM Research Division, Haifa Research Lab), Randall R Pratt, William P Moore (IBM Microelectronics Division, Essex Junction, Vt.)
[abstract]  [manuscript]

DISPS-4.5
Engineering Change Protocols for Behavioral Synthesis
Miodrag Potkonjak, Darko Kirovski (Computer Science Department, University of California, Los Angeles)
[abstract]  [manuscript]

DISPS-4.6
Operation Scheduling for Parallel Functional Units Using Genetic Algorithms
Thomas Zeitlhofer, Bernhard R Wess (INTHFT, Vienna University of Technology)
[abstract]  [manuscript]

DISPS-4.7
Extended Retiming: Optimal Scheduling via a Graph-Theoretical Approach
Timothy W O'Neil, Sissades Tongsima, Edwin H.-M. H Sha (Dept. of Computer Science and Engineering, Univ. of Notre Dame)
[abstract]  [manuscript]

DISPS-4.8
Minimum Initiation Interval of Multi-Module Recurrent Signal Processing Algorithm Realization with Fixed Communication Delay
Hung-Ying Tyan (Electrical Engineering Dept, Ohio State University), Yu Hen Hu (Dept. Electrical & Computer Engr, University of Wisconsin)
[abstract]  [manuscript]

DISPS-4.9
A New Approach for Block-Floating-Point Arithmetic
Shiro Kobayashi, Gerhard P Fettweis (Mobile Communications Systems, EE, Dresden University of Technology)
[abstract]  [manuscript]

DISPS-4.10
The Effects of Finite Bit Precision for a VLSI Implementation of the Constant Modulus Algorithm
Louis R Litwin (Purdue University), Thomas J Endres, Samir N Hulyalkar (Sarnoff Digital Communications), Michael D Zoltowski (Purdue University)
[abstract]  [manuscript]

< DISPS-3

Last Update: February 4, 1999 Ingo Höntsch