Chair: John Ackenhusen, Environmental Research Institute of Michigan (USA)
M. Richards, Advanced Research Projects Agency
R. Reitmeyer, ARL EPSD (USA)
A. Bard, ARL EPSD (USA)
G. Michael, ARL EPSD (USA)
The Rapid Prototyping of Application Specific Signal Processors (RASSP) program is an ARPA/Tri-Service initiative intended to dramatically improve the process by which complex digital systems, particularly embedded digital signal processors, are designed, manufactured, upgraded, and supported. RASSP seeks to improve by at least a factor of four (4x) the time required to take a design from concept to fielded prototype. RASSP is motivated by the need to provide affordable embedded signal processors for a wide range of DoD systems that are state-of-the-art when they are fielded, rather than when they are first defined.
Asawaree Kalavade, University of California at Berkeley (USA)
Jose Luis Pino, University of California at Berkeley (USA)
Edward A. Lee, University of California at Berkeley (USA)
System-level design is characterized by a behavioral specification and heterogeneous hardware/software implementations. Exploring the design space is essential for good design. Specifying and managing complex design flows, tracking dependencies and tool invocations, and maintaining consistency of design data and flows are key issues that enable efficient design space exploration. In order to manage the complexity of this design process, an infrastructure that manages these issues, transparent to the user, is presented. These concepts have been implemented in the Ptolemy environment within a framework called DesignMaker. An example design flow for multiprocessor synthesis is presented in some detail to illustrate the features of DesignMaker. The end objective of the framework is to facilitate a flexible system-level codesign assistant.
Jan Rabaey, University of California at Berkeley (USA)
Lisa Guerra, University of California at Berkeley (USA)
Renu Mehra, University of California at Berkeley (USA)
This work proposes an approach for high level design guidance for low power using properties of given algorithms and architectures. Several relevant properties (operation count, the ratio of critical path to available time, spatial locality, and regularity) are identified and discussed, with quantitative measures being proposed for the latter two. Significant emphasis is placed on exploiting the regularity and spatial locality algorithm properties for the optimization of interconnect power. Examples illustrate the large savings that can be attained through property-based guidance of algorithm selection and architecture composition. Though demonstrated for ASIC designs, this approach is extensible to different hardware platforms and performance metrics (e.g. speed, area).
Benjamin Friedlander, University of California (USA)
MAT2DSP is a MATLAB toolbox, currently under development, whose function is to estimate the implementation requirements of algorithms specified in the form of a MATLAB program. This toolbox is aimed at providing researchers developing advanced signal and image processing algorithms, a quick and convenient way of estimating what would be needed to implement their algorithm on a specified processor. MAT2DSP analyzes the user program and generates reports on its computational requirements.
Panos Papamichalis, Texas Instruments (USA)
Jay Reimer, Texas Instruments (USA)
Jon Rowlands, Texas Instruments (USA)
The widespread use of DSP techniques in many signal processing applications has made algorithm implementations a task that engineers face frequently. However, the real-time constraints that most of these applications have, often clash with the need to do the implementation quickly and with minimal pain. This paper examines tools and techniques that have been created for and applied on the TMS320 family of digital signal processors to facilitate such development. The use of C compilers speeds up the implementation, while software and hardware development tools make debugging easier. Some techniques of algorithm implementation are examined in the context of specific applications.
Chaitali Chakrabarti, Arizona State University
Mohan Vishwanath, Xerox Palo Alto Research Center
Robert M. Owens, Pennsylvania State University (USA)
Wavelet transforms have proven to be useful tools for several applications, including signal analysis, signal coding, and image compression. This paper surveys the VLSI architectures that have been proposed for computing the Discrete and Continuous Wavelet Transforms for 1-D and 2-D signals. The proposed architectures range from SIMD arrays to folded architectures such as systolic arrays and parallel filters. The SIMD arrays have a size that is proportional to that of the data sequence and are optimal with respect to time. The folded architectures, on the other hand, support single chip implementations and are optimal with respect to both area and time under the word-serial model.
Yu Hen Hu, University of Wisconsin (USA)
Optimal VLSI array structure design for the implementation of vector quantization (VQ) are investigated in this paper. After a brief review of the VQ algorithms, the algorithm and architecture design issues will be discussed. This is followed by a brief survey existing VQ implementation strategies and architecture.
S. Hamid Nawab, Boston University (USA)
Joseph M. Winograd, Boston University (USA)
A framework for approximate signal processing is introduced which can be used to design novel classes of algorithms for performing DFT and STFT calculations. In particular, we focus on the derivation of multi-stage incremental refinement algorithms that meet a variety of design criteria on the tradeoff achieved at each stage between solution quality and computational cost.
Graham A. Jullien, University of Windsor (CANADA)
This paper reviews recent strategies in implementing DSP systems using residue computations; in particular we highlight current work underway in the VLSI Research Group, at the University of Windsor, in the area of high throughput DSP systems on silicon. The paper reviews a series of issues including recently disclosed mapping techniques, fault tolerant architectures, and area power efficient VLSI implementation procedures. CAD tools, developed for automating the desing and layout of residue DSP systems on silicon, are also discussed. An extensive bibliography is provided for further reading.
James R. Armstrong, Virginia Tech (USA)
complicated, labor-intensive task. Also, tests generated manually satisfy no formal definition of completeness. To address these needs, high level approaches to test bench level development are employed which relieve the modeler of this task. CASE tools are used to develop the test bench VHDL code, i.e., state machine behavior is specified with Ilogix Express VHDL and sensor behavior with Comdisco SPW. An intelligent interface prompts the user for high level test bench information, and inserts this information into the test bench code. The intelligent interface also allows the user to specify and control file I/O as a data source. Conceptually speaking, two approaches are being explored: 1)behavioral-the CASE tools develop complete high level models of the test bench, and 2) structural- a library of primitive components is developed so that a conventional schematic capture tool, e.g., Synopsys Graphical Environment, can be used to con- struct the test bench.