Chair: Wanda Gass, Texas Instruments (USA)
J.G. Ackenhusen, Environmental Research Institute of Michigan
Q.A. Holmes, Environmental Research Institute of Michigan
P.A. Kortesoja, Environmental Research Institute of Michigan
D.L. McCubbrey, Environmental Research Institute of Michigan
P.L. Mohan, Environmental Research Institute of Michigan
J.A. Salinger, Environmental Research Institute of Michigan
T.N. Wessling, Environmental Research Institute of Michigan
L.J. Witter, Environmental Research Institute of Michigan
H. Stopper, Pico Systems (USA)
A processor that applies a heterogeneous architecture to the problem of image recognition has been developed. Several unique features distinguish this work from other work in this field and are the subject of this paper: 1) use of a complete set of documented applications of automatic target recognition to derive and validate processor requirements; 2) choice of a heterogeneous architecture that integrates several types of processors; 3) development of image-processing-domain custom integrated circuits; 4) application of wafer-scale multichip module miniaturization to the image processing pipeline; and 5) use of a piecewise-connected hierarchy of simulation tools, providing for connectivity of simulation both vertically (i.e. from chip through boards to subsystem) and horizontally (i.e. board vs. multichip module domain). This processor has been programmed with several recognition algorithms and delivered in a baseline 20-stage-pipeline-configuration, where it achieves over 20 billion RISC-equivalent operations/sec upon 16-bit pixels.
W.Y. Kan, Purdue University (USA)
J.V. Krogmeier, Purdue University (USA)
P.C. Doerschuk, Purdue University (USA)
Accurate and wide-area estimates of vehicle velocity and traffic spatial and temporal densities will be essential components of future algorithms for freeway and arterial street control, for incident prediction and detection, and for optimization in route selection. Algorithms like these figure prominently in the current research and development of Intelligent Vehicle-Highway Systems (IVHS). This paper presents an approach to a class of vehicle monitoring problems which is based upon a video backbone sensor and multiple target tracking (MTT). The method allows the integration of measurements made from other sensors like inductive loops, microwave radars, and laser range profilers.
Agus Trihandoyo, Universite de Technologie de Compiegne (FRANCE)
Adam Belloum, Universite de Technologie de Compiegne (FRANCE)
Kun-Mean Hou, Universite de Technologie de Compiegne (FRANCE)
Achieving reliable implementation of a real-time speaker independent speech recognizer through the telephone network is a challenging research problem. Besides requiring the selection of a suitable algorithm, which takes into account both real-time and accuracy constrains, it requires also adequate hardware architecture and optimized software. This paper presents a dedicated multiprocessor DSP architecture for telecom applications. Based on ADSP-21060 SHARC DSPs, it is the kernel of a digital interactive voice response (IVR) system that is connected to a digital switch through the primary CCITT standard time division multiplexing line of 2.048 Mbps. We attempt to show how a multi-DSP based hardware can be designed for a specific problem in telecommunication, along with the implementation of automatic speech recognition (ASR) to the digital IVR system.
Masashi Naitoh, Kokusai Electric Co. Ltd. (JAPAN)
Mitsuo Kubo, Kokusai Electric Co. Ltd. (JAPAN)
Kenzo Urabe, Kokusai Electric Co. Ltd. (JAPAN)
This paper investigates the experimental performance of the recursive least square adaptive algorithm-maximum likelihood sequence estimation equalizer (RLS-MLSE) implemented in a single DSP for application to the Japanese PDC (Personal Digital Cellular) system under a harsh frequency-selective-fading environment. Frame synchronization and automatic frequency control (AFC) play important role to make the equalizer effective, because the performance impairment of those functions causes serious degradation of the equalizer performance. In order to improve total system performance under frequency-selective-fading, we apply a new high precision frame synchronization scheme using recursive least square (RLS) algorithm and also a new AFC algorithm scheme taking advantage of a replica of distorted unique word (UW). In the Rayleigh faded two-wave model with one symbol delay, 1% BER can be achieved at Eb/N0 equal to 16.0 dB with a maximum Doppler frequency equal to 40 Hz.
Jack H. Corley, South Carolina Research Authority
Vijay K. Madisetti, Georgia Institute of Technology
Mark A. Richards, Advanced Research Projects Agency (USA)
The Rapid Prototyping of Application Specific Signal Processors (RASSP) U.S. Department of Defense (ARPA/Tri-Services) initiative is intended to dramatically improve the way digital systems, particularly embedded digital signal processors, are designed, manufactured, upgraded, and supported. These DSP systems are complex, with typically one or more printed circuit boards, a variety of implementation technologies and interfaces, and a wide range of data rates. The target RASSP improvement is at least a fourfold (4x) reduction in the time to go from design concept to fielded system. Equivalent improvements in cost and quality are also targets. The motivation for the RASSP initiative is the pervasive need for affordable embedded signal processors throughout a wide range of DoD systems, signal processors that are state-of-the-art when they are fielded rather than when they are first defined. A number of programs are included in the RASSP initiative. This paper introduces the initiative from both technical and programmatic viewpoints.
Cory Myers, Lockheed Sanders Inc. (USA)
Ray Dreiling, Lockheed Sanders Inc. (USA)
This paper presents modeling approaches and experiences in the use of the VHSIC Hardware Description Language (VHDL) for the development of application-specific signal processors. Within our work on the ARPA/Tri-Service RASSP program we have developed and used VHDL modeling techniques for modeling the performance of signal processor systems and for the detailed design of signal processor systems. These approaches have been applied to modeling a large Infra-Red Search and Track system from a functional model, through performance modeling, through a full functional model, down to a detailed hardware implementation model.
G. Caracciolo, Martin Marietta Laboratories (USA)
J. Pridmore, Martin Marietta Laboratories (USA)
The Rapid Prototyping of Application Specific Signal Processors (RASSP) program is striving to change the way embedded signal processor design is performed, providing >4X improvements in time- to-market, cost, and design quality. These improvements will be achieved using a methodology that stresses hardware and software reuse in conjunction with Model Year Architectures that facilitate reusability and upgradability through open interface standards. This paper will describe a Model Year Architecture (MYA) approach for the development of cost effective signal processors that can be applied to a wide range of military and commercial applications.
G.A. Shaw, MIT Lincoln Laboratory
J. C. Anderson, MIT Lincoln Laboratory
V.K. Madisetti, Georgia Institute of Technology (USA)
The Department of Defense ARPA program for Rapid Prototyping of Application Specific Signal Processors (RASSP) exists to significantly improve the process by which embedded digital signal processors are developed (prototyped) and supported (maintained and upgraded). As used in the RASSP program, the term prototype signifies a system that is a precursor to a deployed system, but still meets all of the essential performance goals and is designed to facilitate maintainability and upgradability. In this paper, current practice in the design of embedded digital signal processors, as exemplified in the traditional waterfall design methodology, is examined and shortfalls in the design methodology and supporting tools are identified. Opportunities for improving the traditional design practice are then identified and evaluated in terms of potential benefits, as well as impediments, to implementation and adoption by the community.
Vijay Madisetti, Georgia Institute of Technology (USA)
Thomas W. Egolf, Georgia Institute of Technology (USA)
S. Famorzadeh, Georgia Institute of Technology (USA)
L-R. Dung, Georgia Institute of Technology (USA)
The Rapid Prototyping of Application Specific Signal Processors (RASSP) program initiated by the Advanced Research Projects Agency (ARPA) has proposed a design process that is based on a new design methodology called Virtual Prototyping, wherein VHDL models of hardware components are integrated with application, control and diagnostic software to rapidly prototype complex embedded DSP systems. This paper discusses this new methodology, and compares the RASSP process with current design practice (circa 1993).
Joseph M. Winograd, Boston University (USA)
S. Hamid Nawab, Boston University (USA)
A new environment for the rapid development of embedded signal processing software is described. The environment encourages incremental design via modular and hierarchical structuring of applications, and additional features are included which support the prototyping, testing, implementation, and integration stages of the system design cycle. Written in C++, the environment is comprised of a scripting language for the definition of system components and a class library which includes a basic application framework. Support is provided for incorporating both numeric and symbolic signal representations, as well as integrating multiple signal processing techniques within a single application. A sophisticated control mechanism allows dynamic scheduling of signal processing operations according to algorithmically defined schema. Signal processing applications developed in this environment are themselves objects, and are suitable for embedding within a larger overall system.