Title:    DSP Development Tools   (Lecture)

Time: Thursday, March 18, 9:30 AM - 11:30 AM

Location:    Tucson 4

Chair: Keshab Parhi    (University of Minnesota)

9:30 AM    DISPS-1.1
High-level Modeling of Switching Activity With Application to Low-power DSP System Synthesis
Magnus Lundberg (Lulea University of Technology, Lulea, Sweden), Khurram Muhammad, Kaushik Roy (Purdue University, West Lafayette, IN 47907), Sarah Kate Wilson (Lulea University of Technology, Lulea, Sweden)
[abstract]  [manuscript]

9:45 AM DISPS-1.2
Activity Models for use in Low Power, High-Level Synthesis
Russell E. Henning, Chaitali Chakrabarti (Dept of Electrical Engineering, Arizona State University, Tempe, AZ 85287)
[abstract]  [manuscript]

10:00 AM DISPS-1.3
Multirate as a Hardware Paradigm
Bruce W Suter (Air Force Research Laboratory), Kenneth S Stevens (Intel), Scott R Velazquez (V Company), Truong Nguyen (Boston University)
[abstract]  [manuscript]

10:15 AM DISPS-1.4
Unfolding Probabilistic Data-flow Graphs Under Different Timing Models
Sissades Tongsima, Timothy W O'Neil, Edwin Sha (Dept. of Computer Science and Engr., University of Notre Dame)
[abstract]  [manuscript]

10:30 AM DISPS-1.5
Low-power Channel Coding via Dynamic Reconfiguration
Manish Goel, Naresh R Shanbhag (University of Illinois at Urbana-Champaign)
[abstract]  [manuscript]

10:45 AM DISPS-1.6
Closed-Form and Real-Time Wordlength Adaptation
Paul D Fiore (Sanders, A Lockheed Martin Co.), Li Lee (Massachusetts Institute of Technology)
[abstract]  [manuscript]

11:00 AM DISPS-1.7
Synthesis of DSP Soft Real-Time Multiprocessor Systems-on-Silicon
Darko Kirovski, Miodrag Potkonjak (COMPUTER SCIENCE DEPARTMENT, UNIVERSITY OF CALIFORNIA, LOS ANGELES)
[abstract]  [manuscript]

11:15 AM DISPS-1.8
A Generic Methodology for the Software Managing of Caches in Multi-Processors DSP Architectures
Frantz LOHIER, Lionel Lacassagne (EIA/LIS), Patrick Garda (LIS)
[abstract]  [manuscript]

DISPS-2 >

Last Update: February 4, 1999 Ingo Höntsch