3:30, SPEC-L3.1
IMPLEMENTATION OF FIXED DSP FUNCTIONS USING THE REDUCED COEFFICIENT MULTIPLIER
R. TURNER, T. COURTNEY, R. WOODS
Distributed Arithmetic (DA) has been successfully applied to the design of area efficient multipliers on FPGAs for DSP applications. Whilst DA is efficient in applications where coefficients are fixed, there is little option for applications with a limited range of coefficient values. This paper describes a technique for developing area-efficient multipliers for a range of DSP applications that fall into this category. This is accomplished by employing multiplexers at no extra cost to increase the functionality of existing fixed coefficient multipliers. The technique has been applied to a DCT FPGA implementation where an area decrease of up to 50% and speed increase of 33% was achieved over the conventional route.

3:50, SPEC-L3.2
GIGAOP DSP ON FPGA
B. HUTCHINGS, B. NELSON
DSP algorithms such as sonar beamforming and automated target recognition, are a good match for FPGA technology due to their regular structure, available parallelism, pipeline- ability, and modest data word sizes. FPGA implementations of these applications outperformed their DSP and micropro- cessor counterparts by factors ranging from 10X on up with an equivalent sustained computational rate of more than 2 GOps/second per FPGA. This paper first describes each application and derives its computational requirements. The mapping process for each is then described followed by an analysis of the relative contributions to performance from pipelining, data parallelism, and memory usage.

4:10, SPEC-L3.3
MAXIMUM LIKELIHOOD CARRIER PHASE SYNCHRONIZATION IN FPGA-BASED SOFTWARE DEFINED RADIOS
M. RICE, C. DICK, F. HARRIS
Digital signal processing techniques are applied to maximum likelihood carrier phase synchronization for QPSK and QAM in an all-digital sampled data receiver. To achieve the flexibility required by modern Software Defined Radios (SDR's), this task must either be performed in a DSP processor (reconfigurable software) or in an FPGA (reconfigurable hardware). This paper describes the design process for an FPGA-based design and summarizes the FPGA resources required for QPSK carrier phase synchronization.

4:30, SPEC-L3.4
RECONFIGURABLE PLATFORM DESIGN FOR WIRELESS PROTOCOL PROCESSORS
T. TUAN, S. LI, J. RABAEY
Low-energy protocol processing is a crucial issue in next -generation wireless systems. In modern wireless system design, this problem is tightly coupled with the signal processing needs. Fierce market competition and inventive wireless applications are imposing stricter design requirements in energy consumption, cost, size, and flexibility. To deal with these unique constraints, we incorporate the platform -based design methodology to deal with these constraints by advocating reusability. This paper presents this methodology, and its application on PicoRadio, a cutting -edge wireless system. In particular, we describe the design of a reconfigurable architecture optimized for protocol processing.

4:50, SPEC-L3.5
PARAMETERISED FLOATING-POINT ARITHMETIC ON FPGAS
A. JAENICKE, W. LUK
This paper describes the parameterisation, implementation and evaluation of floating-point adders and multipliers for FPGAs. We have developed a method, based on the Handel-C language, for producing technology-independent pipelined designs that allow compile-time parameterisation of design precision and range, and optional inclusion of features such as overflow protection, gradual underflow and rounding modes of the IEEE floating-point format. The resulting designs, when implemented in a Xilinx XCV1000 device, achieve 28 MFLOPs with IEEE single precision floating-point numbers. These designs are used in an optimised implementation for computing Two-Dimensional Fast Hartley Transform. Preliminary results suggest that our implementation is faster than many programmable DSP processors and supercomputers.

5:10, SPEC-L3.6
DYNAMICALLY PARAMETERIZED ALGORITHMS AND ARCHITECTURES TO EXPLOIT SIGNAL VARIATIONS FOR IMPROVED PERFORMANCE AND REDUCED POWER
W. BURLESON, R. TESSIER, D. GOECKEL, S. SWAMINATHAN, P. JAIN, J. EUH, S. VENKATRAMAN, V. THYAGARAJAN
Signal processing algorithms and architectures can use dynamic reconfiguration to exploit variations in signal statistics with the objectives of improved performance and reduced power consumption. Parameters provide a simple and formal way to characterize incremental changes to a computation and its computing mechanism. This paper examines five parameterized computations which are typically implemented in hardware for a wireless multimedia terminal: 1) motion estimation, 2) discrete cosine transform, 3) Lempel-Ziv lossless compression, 4) 3D graphics light rendering and 5) Viterbi decoding. Each computation is examined for the capability of dynamically adapting the algorithm and architecture parameters to variations in their respective input signals. Dynamically reconfigurable low-power implementations of each computation are currently underway.