9:30, ITT-L2.1
DESIGN AND IMPLEMENTATION OF A MIXED SIGNAL EMBEDDED DSP SYSTEM
M. YEARY, D. GUIDRY, M. BURNS
At Texas Instruments, integrated circuits in production are continually becoming more power efficient and faster. The time associated with testing these designs, say with a with Taradyne test platform, represents a large cost of the overall price of these integrated circuits. This paper discusses the design and layout of a compact mixed signal printed circuit board using a digital signal processor (DSP) that can be used in the test environment. In general, we live in an analog world, but the processing and transfer of information is typically digital. Mixed signal designs offer the best of both worlds since these designs can take advantage of the processing power of a DSP, while operating in close proximity to the analog signals. The paper presents a discussion of our design along with a picture of our mixed signal board, more detailed discussions and pictures may be viewed at $~~$ http://ee.tamu.edu/~mbyeary/mixedsignal.html

9:50, ITT-L2.2
VECTOR PROCESSING IN SCALAR PROCESSORS FOR SIGNAL PROCESSING ALGORITHMS
M. BRADY, J. TRELEWICZ, J. MITCHELL
Product requirements often dictate the use of off-the-shelf processors for very fast signal processing applications. Additionally, restrictions on cost, power, or size/weight may preclude the use of specialized vector processors for implementation of the algorithms. We discuss a new method for performing signed parallel processing in scalar, off-the-shelf processors for integerized signal processing algorithms. Uniform data precision may be used, but is not required for the method. It is shown that the reduction in execution cycles resulting from this implementation is approximately linear in the size of the registers, divided by the precision required.

10:10, ITT-L2.3
A PROGRAMMABLE PROCESSOR WITH 4096 PROCESSING UNITS FOR MEDIA APPLICATIONS
A. KRIKELIS, I. JALOWIECKI, D. BEAN, M. FACEY, D. BOUGHTON, S. MURPHY, M. WHITAKER
This paper presents the architecture of the Linedancer DSP processor. The Linedancer provides high multimedia performance with low energy consumption by integrating associative SIMD parallel processing with embedded microprocessor technology. The major innovations in the Linedancer is the integration of thousands of processing units, i.e. 4096, in a single chip that are capable to support software programmable high-performance mathematical functions as well as abstract data processing. The Linedancer, compared with other DSP approaches, offers true performance scalability, support for deterministic and non-deterministic data processing on a single device, and software programmability that can be re-used in future chip generations.

10:30, ITT-L2.4
A SINGLE-CHIP MPEG-2 MP@ML AUDIO/VIDEO ENCODER/DECODER WITH A PROGRAMMABLE VIDEO INTERFACE UNIT
C. CHEN, T. CHEN, F. JENG, H. CHENG, K. KONSTANTINIDES
We present a single-chip, MPEG-2 Main Profile at Main Level , audio and video encoder and decoder. It combines a RISC core, a 24-bit DSP, video and audio interface units, and several dedicated processing units. A programmable video interface unit supports multiple modes of pre- and post-processing and on-screen display (OSD). The codec has been implemented using a standard-cell library in 0.18 um CMOS technology.

10:50, ITT-L2.5
EFFICIENT IMPLEMENTATION OF VIDEO POST-PROCESSING ALGORITHMS ON THE BOPS PARALLEL ARCHITECTURE
D. PETRESCU
Deblocking and deringing are two well known video post-processing techniques used to remove coding artifacts and improve the visual quality when rendering low bitrate video. The algorithms used to achieve these tasks are computationally intensive and usually require high speed processors to be able to run in real time. Efficient implementations of signal adaptive filters for video post-processing can be obtained using the specialized features of the parallel BOPS DSP cores. The performance achieved by deblocking and deringing CIF and SDTV size video sequences on the MANTA prototype chip are illustrated. It is shown that such complex tasks may be executed at low clock rates using the BOPS ManArray technology (http://www.bops.com).

11:10, ITT-L2.6
VSIPL: AN OBJECT-BASED OPEN STANDARD API FOR VECTOR, SIGNAL, AND IMAGE PROCESSING
J. LEBAK, R. JANKA, R. JUDD, M. RICHARDS, D. CAMPBELL
VSIPL, the Vector, Signal, and Image Processing Library, is an open standard application programmer's interface (API) for signal and image processing. Defined by a consortium of industry, government, and academic representatives, VSIPL is gaining widespread acceptance as a de facto standard in the embedded signal processing world. The primary goal of the API is to increase the portability of vector signal processing, matrix signal processing, and image processing applications. In this paper, we present an overview of the design, features, and availability of the VSIPL API.