Chair: K.J.Ray Liu, University of Maryland (USA)
Miodrag Potkonjak, University of California at Berkeley (USA)
Jan M. Rabaey, University of California at Berkeley (USA)
We introduce the algorithm selection problem for power minimization. After demonstraing a high impact of this synthesis task on the power consumption of the final implementation using case study, we studied its computational complexity. We present an efficient optimization intensive algorithm for power minimization using algorithm selection. On several DSP examples more than an order of magnitude reduction in power is demonstrated.
Jose Luis Pino, University of California at Berkeley (USA)
Edward A. Lee, University of California at Berkeley (USA)
In this paper we discuss a hierarchical scheduling framework to reduce the complexity of scheduling synchronous dataflow (SDF) graphs onto multiple processors. The core of this framework is a clustering technique that reduces the number of actors before expanding the SDF graph into a directed acyclic graph (DAG). The internals of the clusters are then scheduled with uniprocessor SDF schedulers which can optimize for memory usage. The clustering is done in such a manner as to leave ample parallelism exposed for the multiprocessor scheduler. We illustrate this framework with a real-time example that has been constructed in Ptolemy.
Markus Willems, Aachen University of Technology (GERMANY)
Matthias Pankert, Aachen University of Technology (GERMANY)
Sebastian Ritz, Aachen University of Technology (GERMANY)
Code generation for a system specified by a block diagram facilitates the fast and efficient evaluation of the design space. As a drawback, automatically generated code includes a certain amount of data management overhead compared to handwritten code, especially when the block diagram includes fine granular structures. Within this paper we present a strategy how to overcome certain types of overhead by introducing a novel code generation approach. While traditional tools are based on a one-to-one correspondence between a block on the block diagram level and a functional kernel on the code synthesis level, now one new functional kernel for a group of blocks is generated automatically. Doing so, a maximum of dataflow information available from the block diagram level is employed to organize the kernel in an efficient way, regarding to the designer's criterion. As a result, reduction in memory consumption and an increased throughput can be achieved jointly.
Sebastian Ritz, RWTH (GERMANY)
Markus Willems, RWTH (GERMANY)
Heinrich Meyr, RWTH (GERMANY)
For the design of complex digital signal processing systems, block diagram oriented synthesis of real time software for programmable target processors has become an important design aid. The synthesis approach discussed in this paper is based on multirate block diagrams with scalable synchronous dataflow (SSDF) semantics. For this class of dataflow graphs we present scheduling techniques for optimum data memory compaction. These techniques can be employed to map signals of a block diagram onto a minimum data memory space. In order to formalize the data memory compaction problem, we first derive appropriate implementation measures. For the class of single appearance (SA) block diagrams with SSDF semantics, scheduling can be reduced to an integer linear programming (ILP) problem. Due to the computational complexity of ILP, we also present a suboptimum scheduling selection criterion, which can be used for SA and non SA-schedulers.
Yin-Hwa Huang, Ministry of Transportation & Communication (REPUBLIC OF CHINA)
Yuo-Chuan Chang, Ministry of Transportation & Communication (REPUBLIC OF CHINA)
Chi-Shyan Wu, Ministry of Transportation & Communication (REPUBLIC OF CHINA)
Chien-Hsing Wu, Ministry of Transportation & Communication (REPUBLIC OF CHINA)
In this paper, we present the design of an MPEG-based set-top box for digital video decoding and interfacing with the ADSL-based network or fiber-coaxial network. The architecture of the set-top box consists of three major functional blocks: the central control unit, the digital video decoding unit and network interface unit. A universal bus is used to connect these blocks and other add-on peripheral modules. Based on this bus,an extension slot is implemented to enhance the design flexibility in supplementing functionality and upgrading performance, such as the improvement from the original 1.544 Mbps T1 interface to a higher throughput network interface in order to provide high quality MPEG II video on demand (VOD) services.
Jan M. Rabaey, University of California at Berkeley
Miodrag Potkonjak, NEC Corporation (USA)
Kazutoshi Wakabayashi, NEC Corporation (USA)
We present a generalized Horner's scheme-based approach which enables that a large and important subclass of nonlinear computations, named feedback linear computations, is efficiently, maximally, and arbitrarily sped-up. The new class includes popular nonlinear polynomial Volterra filters and widely used LMS and RLS adaptive filters. The effectiveness and low overhead of the proposed techniques is illustrated on several designs.
Zhongmin Yu, Hokkaido University (JAPAN)
Yoshinao Aoki, Hokkaido University (JAPAN)
Embedded computers (EC) have been used widely in the world, however, embedded computer software is often difficult to develop for the lack of suitable debugging environment. With the traditional in-circuit debugging method, it is difficult to analyze the reason of error; also it is impossible to debug a software before the implementation of associated hardware; moreover, it costs both money and time to create the hardware, so that it can hardly keep up with the ever-changing of a great number of ECs. To tackle the problem, we have made research on the prototyping method for simulation debugging environment (SDE) of embedded computer software. Our purpose is to establish an environment to construct SDE and use the software SDE to substitute the traditional in-circuit debugging environment. By the method, users can construct a SDE at a higher speed and lower cost, the development efficiency for embedded computer software will also be increased greatly.
M. Li, University College of Swansea (UK)
J.T. Proudfoot, University College of Swansea (UK)
G. King, University College of Swansea (UK)
The high level design and specification of an application specific integrated circuit is described which implements a pattern matching algorithm based on Vector Quantization and a speaker identification algorithm. For pattern matching , the VQ codebook structure, search and Euclidean distance measure are discussed. The mapping into three ASIC devices is explained and justified together with details of the ELLA design methodology used. The architecture of the pattern matching and logic decision circuits is then developed. Based on a single processor multiplexed ten ways, the recursive design has been tested by high level functional simulation. Test vectors derived by extracting parameters from real data have produced the results reported in concluding the paper.
Tomohiro Nakatani, NTT Basic Research Laboratories (JAPAN)
Takeshi Kawabata, NTT Basic Research Laboratories (JAPAN)
Hiroshi G. Okuno, NTT Basic Research Laboratories (JAPAN)
This paper presents a new computation model for sound stream segregation based on a multi-agent paradigm. Sound streams are thought to play a key role in auditory scene analysis, which provides a general framework for auditory research including voiced speech and music. Since various kinds of sounds appear dynamically in the real-world, an adaptive mechanism is required for sound stream segregation. In our system, each agent is dynamically allocated to a sound stream, and it extracts the stream by focusing on consistent attributes. Agents interact with each other to resolve stream interference. As a whole, the system adaptively segregates individual sound streams. This paper reports on the design of agents to segregate harmonic streams and a noise stream. The presented system can segregate all the streams from a mixture of a male and a female voiced speech and a background non-harmonic noise.
Anthony G. Place, James Cook University (AUSTRALIA)
Gregory H. Allen, University of Westminster (UK)
It is well known that the actual poles implemented in digital filters are increasingly sensitive to decreasing pole separation and that practical filters are implemented usually as a cascade of second order sections or the dual form to avoid this sensitivity. This paper considers the case of filters implemented in direct form and having localised poles. Expressions that describe pole position sensitivity for simple isolated poles and for multiple poles have previously been developed. This paper addresses the final problem of pole sensitivity due to pole interaction when one or more poles are placed in "close proximity" to other poles.